conv_std_logic_vector() - std_logic_arith

These functions convert the arg argument to a std_logic_vector value with size bits.
If arg is unsigned or positive, it is treated as an unsigned value; if it is negative, it is converted to 2's complement signed form.

Syntax

function conv_std_logic_vector(arg: integer, size: integer) return std_logic_vector;
function conv_std_logic_vector(arg: unsigned, size: integer) return std_logic_vector;
function conv_std_logic_vector(arg: signed, size: integer) return std_logic_vector;
function conv_std_logic_vector(arg: std_ulogic, size: integer) return std_logic_vector;

Example

signal u1 : unsigned (3 downto 0);
signal s1 : signed (3 downto 0);
signal v1, v2, v3, v4 : std_logic_vector (3 downto 0);
signal i1, i2 : integer;
...
u1 <= "1101";
s1 <= "1101";
i1 <= 13;
i2 <= -3;
wait for 10 ns;
v1 <= conv_std_logic_vector(u1, 4);   -- = "1101" 
v2 <= conv_std_logic_vector(s1, 4);   -- = "1101" 
v3 <= conv_std_logic_vector(i1, 4);   -- = "1101" 
v4 <= conv_std_logic_vector(i2, 4);   -- = "1101"

Output / Return Value

Limitations

Alternatives / See Also

Reference

https://www.cs.sfu.ca/~ggbaker/reference/std_logic/arith/conv_std_logic_vector.html